The electrical transmission links by way of which input terminals of an operational amplifier are coupled to upstream circuitry normally include resistive current paths, thereby resulting in an IR drop across such paths which alters or shifts the actual voltage levels expected to be seen at the amplifier input terminals. It is desirable, therefore, to minimize the DC input current drawn by the amplifier and thereby improve its performance. One scheme for reducing the input current employs a Darlington-connected transistor pair, with the input transistor of the Darlington pair being biased at a very low current level. Unfortunately, this low level biasing approach dramatically reduces the signal response of the circuit for large magnitude inputs.
More particularly, with attention directed to FIGS. 1 and 2 of the drawings, there are shown respectively a schematic illustration of a Darlington-connected pair of bipolar transistors Q1 and Q2 coupled between an input terminal IN and a bias current sink 42, and the topological integration of the transistors Q1 and Q2 in a dielectric isolated region 20 in a semiconductor wafer.
The Darlington pair is comprised of an input NPN transistor Q1, the base 12 of which is connected via link 10 to an input terminal IN. The collector 11 of transistor Q1 is connected in common with the collector 21 of NPN transistor Q2 and to a collector bias link 31. The emitter 13 of transistor Q1 is coupled via a link 32 to the base 22 of transistor Q2. The emitter of transistor Q2 is coupled via a link 34 to a current sink I2'. The connection of the emitter of transistor Q1 and the base of transistor Q2 is denoted by node a and is coupled over link 33 to a current sink (e.g. diode-connected transistor) 42. Links 10, 32, 33 and 34, which are typically formed of conductive interconnect material (e.g. aluminum, doped-polysilicon) disposed atop a dielectric insulator layer (e.g. SiO.sub.2), are illustrated schematically in FIG. 2 to simplify the drawings. Typically, the current sink 42 is disposed in an island region 30 separate and isolated from the island region 20, as shown topologically in FIG. 2. As a result, the link 33 between node a and the current sink region 42 has a substantial length and passes over or is adjacent to a ground track or grounded semiconductor material, to induce a parasitic capacitance C.sub.p between link 33 and ground.
When a large (negative) transient is applied to the input terminal, the response at the emitter 32 (node a) of transistor Q1 will be affected by the voltage developed across parasitic capacitance C.sub.p, which must be discharged. Because, the DC current level for accomplishing this task has been set at a very low level (I.sub.1 ' corresponding to the current sink 42 connected between node a and ground), the response time of the circuit is significantly impaired.
An alternative approach to the low level bias scheme shown in FIGS. 1 and 2 is to substitute a junction field effect transistor (JFET) in place of the bipolar input transistor. At high input temperature operation (+125.degree. C.) however, the JFET limits the input current to only several nanoamperes and its incorporation into the bipolar integrated circuit structure requires an expensive increase in processing complexity.